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25AA040/25LC040/25C040
3.7
Data Protection
3.8
Power-On State
The following protection has been implemented to
prevent inadvertent writes to the array:
? The write enable latch is reset on power-up
? A write enable instruction must be issued to set
the write enable latch
? After a byte write, page write or STATUS register
write, the write enable latch is reset
? CS must be set high after the proper number of
clock cycles to start an internal write cycle
? Access to the array during an internal write cycle
is ignored and programming is continued
? The write enable latch is reset when the WP pin is
low
The 25XX040 powers on in the following state:
? The device is in low-power Standby mode
(CS = 1 )
? The write enable latch is reset
? SO is in high-impedance state
? A low level on CS is required to enter active state
TABLE 3-3:
WRITE-PROTECT FUNCTIONALITY MATRIX
WP
Low
High
High
WEL
X
0
1
Protected Blocks
Protected
Protected
Protected
Unprotected Blocks
Protected
Protected
Writable
STATUS Register
Protected
Protected
Writable
? 2006 Microchip Technology Inc.
DS21204E-page 11
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